1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a structure of a nonvolatile memory cell array suitable to high-density integration.
2. Description of the Background Art
FIG. 2 schematically shows a structure of a memory cell array in a conventional nonvolatile semiconductor memory device. In FIG. 27, the memory cell array includes a plurality of nonvolatile memory cells MC arranged in rows and columns. FIG. 27 shows representatively nonvolatile memory cells MC11, MC12, MC21 and MC22 arranged in two rows and two columns. A predetermined number of memory cells among the memory cells arranged in a column are coupled to a sub-bit line SBL. In FIG. 27, memory cells MC11 and MC21 are connected to a sub-bit line SBL1, and memory cells MC12 and MC22 are connected to a sub-bit line SBL2.
A word line WL is arranged for the memory cells arranged in a row. In FIG. 27, memory cells MC11 and MC12 are connected to a word line WL1, and memory cells MC21 and MC22 are connected to a word line WL2.
A plurality of sub-bit lines arranged extending in the column direction and aligned in the same column. A sub-source line SSL1 commonly connecting the sources of memory cells MC11, MC21, . . . is provided corresponding to sub-bit line SBL1. Likewise, a sub-source line SSL2 commonly connecting the sources of memory cells 12, MC22, . . . is provided corresponding to sub-bit line SBL2. Sub-source lines SSL1 and SSL2 are connected to a source line SL via source-side block select transistors SGS1 and SGS2 receiving on their gates a source-side block select signal SS. Sub-bit lines SBL1 and SBL2 are connected respectively to main bit lines MBL1 and MBL2 via drain-side block select transistors SGD1 and SGD2 receiving on their gates a drain-side block select signal SD.
Main bit lines MBL1 and MBL2 each are arranged corresponding to a memory cell column and are connected to a plurality of sub-bit lines via the block select transistors receiving a drain-side block select signal. Brief description will now be given on operations of the nonvolatile semiconductor memory device shown in FIG. 27.
Referring first to FIG. 28, an operation for writing data into memory cell MC11 will be described. In this case, drain-side block select signal SD is set to H-level, and drain-side block select transistors SGD1 and SGD2 are set to the on state. Further, source-side block select signal SS is set to L-level, and source-side block select transistors SGS1 and SGS2 are set to the off state so that sub-bit lines SSL1 and SSL2 are electrically floated. Word line WL1 is supplied with a programming high voltage Vhh. Unselected word line WL2 maintains L-level. Main bit line MBL1 is supplied with a voltage at the ground voltage level of L-level. Main bit line MBL2 is supplied with a program inhibiting voltage Vh ( less than Vhh).
In memory cell MC11, the drain is connected to sub-bit line SBL1, and is set to the ground voltage level, the source thereof is connected to sub-source line SSL1, and electrically floated, and the control gate is connected to word line WL1, and receives programming high voltage Vhh. In this state, memory cell MC11 is in such a state that a Fowler-Nordheim tunneling current (F-N tunneling current) flows from a drain region to a floating gate, and electrons are accumulated in the floating gate so that the threshold voltage rises. This state in which threshold voltage Vth is raised is called a xe2x80x9cprogrammed statexe2x80x9d.
In memory cell MC12, the drain receives program inhibiting voltage Vh transmitted onto sub-bit line SBL2. In this state, memory cell MC12 is in such a state that a voltage difference (Vhhxe2x88x92Vh) between the drain and the control gate is low, and F-N tunneling current does not flow so that electrons are not injected into the floating gate, and programming of data into memory cell MC is not performed.
This state wherein the programming is not performed corresponds to a state wherein the threshold voltage Vth is low.
Now, a data read operation will now be described with reference to FIG. 29. In the following description, it is assumed that stored information is read out from memory cells MC11 and MC12, which are in the programmed state (high threshold voltage state (Hi-Vth state)) and the non-programmed state (low threshold voltage state (Low-Vth state)), respectively. In this case, drain-side block select signal SD is set to H-level, and drain-side block select transistors SGD1 and SGD2 are turned on so that sub-bit lines SBL1 and SBL2 are electrically connected to main bit lines MBL1 and MBL2, respectively. The source-side block select signal SS is set to H-level, and source-side select transistors SGS1 and SGS2 are turned on so that sub-source lines SSL1 and SSL2 are connected to source line SL. Source line SL is set to ground voltage GND level.
Word line WL1 is supplied with a read voltage Vr intermediate the high and low threshold voltages Hi-Vth and Low-Vth. Main bit lines MBL1 and MBL2 are supplied with a precharge voltage Vp, and sub-bit lines SBL1 and SBL2 are precharged to precharge voltage Vp level via drain-side block select transistors SGD1 and SGD2.
Since memory cell MC11 is in the high threshold voltage state, and has the threshold voltage higher than read voltage Vr, memory cell MC11 maintains the off state, and sub-bit line SBL1 maintains the voltage level of precharge voltage Vp. Memory cell MC12 is in the low threshold voltage state, and is turned on in accordance with read voltage Vr on word line WL1 so that a current flows from sub-bit line SBL2 via sub-source line SSL2 and source-side block select transistor SGS2 to source line SL at the ground voltage GND level, and the voltage level on sub-bit line SBL2 lowers.
Main bit lines MBL1 and MBL2 are provided with sense amplifier circuits, which in turn sense the changes in voltage level of precharge voltage Vp on main bit lines MBL1 and MBL2 (whether a current flows or not) for reading the data of memory cells. The output data of the sense amplifier circuits provided for main bit lines MBL1 and MBL2 is selected according to a column address signal depending on the output bit width of the nonvolatile semiconductor memory device, and the external reading of the memory cell data is performed.
In the foregoing nonvolatile semiconductor memory device, the memory cell of one bit is formed of one transistor (stacked gate type MOS (insulated gate type field effect) transistor) so that an area occupied by one bit of the memory cell can be small, and the memory cell structure is suitable to high-density integrationization.
FIG. 30 schematically shows a planar layout of the memory cell array shown in FIG. 27. In FIG. 30, N-type impurity diffusion layers 1-1 and 1-2 forming sub-source lines SBL1 and SBL2 are arranged in the column direction. N-type impurity diffusion layers 2-1 and 2-2 extending in the column direction and forming sub-source lines SSL1 and SSL2 are arranged alternately with impurity diffusion layers 1-1 and 1-2. Impurity diffusion layers 1-1 and 1-2 are coupled to impurity regions of drain-side block select transistors SGD1 and SGD2 shown in FIG. 27. Likewise, impurity diffusion layers 2-1 and 2-2 are coupled to impurity regions of source-side block select transistors SGS1 and SGS2 shown in FIG. 27.
Conductive layers 3-0-3-n which form word lines WL1-WLn, respectively, are arranged in the direction perpendicular to impurity diffusion layers 1-1, 1-2, 2-1 and 2-2. These conductive layers 3-0-3-n are formed of, e.g., a second level polycrystalline silicon layer.
A low resistance conductive layer 4 extending in the row direction for transmitting drain-side block select signal SG is arranged crossing drain-side block select transistors SGD1 and SGD2. A low resistance conductive layer 5 for transmitting source-side block select signal SS is arranged crossing source-side block select transistors SGS1 and SGS2. A low resistance conductive layer 6 forming source line SL is arranged parallel to conductive layer 5.
Conductive layer 4 functions as gates of drain-side block select transistors SGD1 and SGD2, and conductive layer 5 functions as gates of source-side block select transistors SGS1 and SGS2. The source-side impurity regions of source-side block select transistors SGS1 and SGS2 are electrically coupled to conductive layer 6 forming source line SL through contact holes 8c and 8d, respectively. The impurity regions of drain-side block select transistors SGD1 and SGD2 are electrically connected to low resistance conductive layers 7-1 and 7-2 forming main bit lines MBL1 and MBL2 through contact holes 8a and 8b, respectively. Low resistance conductive layers 7-1 and 7-2 forming main bit lines MBL1 and MBL2 extend in the column direction and are arranged in the direction crossing conductive layers 4, 5 and 6. Low resistance conductive layers 7-1 and 7-2 forming main bit lines MBL1 and MBL2 are formed of an interconnection layer higher than conductive layers 4, 5 and 6.
FIG. 31 schematically shows a sectional structure of memory cell MC. Memory cell MC includes heavily doped N-type impurity regions (N-type impurity diffusion layers) 1 and 2 formed at the surface of a P-type semiconductor substrate region 9, a conductive layer 10 formed on a channel region between impurity diffusion regions 1 and 2 and forming a floating gate FG, and conductive layer 3 formed on conductive layer 10 and forming word line WL. Conductive layer 10 forming floating gate FG as well as conductive layer 3 forming word line WL are formed, e.g., of first and second level polycrystalline silicon interconnection layers.
Above conductive layer 3 forming the word line, there is arranged a low resistance conductive layer 7 formed of, e.g., a first level aluminum interconnection layer and forming main bit line MBL. Impurity diffusion layers 1 and 2 are arranged commonly to a predetermined number (n) of memory cells arranged along the column direction. The channel regions of the memory cells in adjacent rows are isolated from each other by an impurity region (not shown). More specifically, field insulating films are formed between word lines WL1-WLn in FIG. 30. Even in the structure wherein the impurity diffusion layer forming the source and drain of each memory cell extends commonly to the plurality of memory cells, each memory cell can individually perform the information storage and data reading in accordance with the signal potential on a corresponding word line WL (WL1-WLn).
As shown in FIGS. 30 and 31, the diffusion layer is utilized for sub-bit line SBL and sub-source line SSL, whereby the following advantages can be provided. If the sub-bit line and sub-source line are formed of, e.g., aluminum interconnection lines, it would be necessary to form contact holes connecting the drain and source of memory cell MC to the first level aluminum interconnection lines forming the sub-bit line and sub-source line, respectively. Therefore, a region for forming the contact holes would be required for every memory cell, resulting in increase in area occupied by the memory cells. By utilizing the diffusion layer as sub-bit line SBL and sub-source line SSL, such contact holes are not required, and the area occupied by the memory cells can be reduced.
If sub-bit line SBL and sub-source line SSL are formed of the first level aluminum interconnection line, main bit line MBL must be formed of an interconnection line at a higher level such as a second level aluminum interconnection line. In this case, the impurity regions (impurity diffusion layers) of the drain-side block select transistors SGD1 and SGD2 are distant from main bit line MBL so that a region for making the contact increases (e.g., a filling plug is required), and the area occupied by the drain-side block select transistors would be increased. By employing such a structure that sub-bit line SBL and sub-source line SSL are formed of the impurity diffusion layer instead of the metal interconnection layer, main bit line MBL can be formed of, e.g., the first level aluminum interconnection layer, whereby it is possible to reduce an area occupied by the contact region between the main bit line and the impurity region of the drain-side block select transistor, and an area occupied by the drain-side block select transistors can be reduced. Thus, the memory cell array area can be reduced, and it is possible to provide the nonvolatile semiconductor memory device having a highly integrated, high-density structure.
FIG. 32 schematically shows a structure of memory cells of two bits arranged in the row direction. In FIG. 32, N-type impurity regions (impurity diffusion layers) 1a, 2a, 1b and 2b are formed at the surface of semiconductor substrate region 9. Between impurity diffusion layers 2a and 1b, there is formed a cell isolating film 11 formed of, e.g., a filed insulating film. A conductive layer 10a forming a floating gate (FG) is formed on the surface of substrate region 9 between impurity regions 1a and 2a, and a conductive layer 10b forming the floating gate is formed on a channel region between impurity regions 1b and 2b. Conductive layer 3 extending in the row direction to form word line WL is formed on conductive layers 10a and 10b forming the floating gates. Conductive layers 7a and 7b extending in the column direction to form main bit lines MBL are formed on conductive layer 3 forming word line WL.
The pitch of memory cells MC in the column direction can be reduced in accordance with the design size. It is merely required to achieve a sufficiently small sheet resistance of impurity diffusion layers 1a, 2a, 1b and 2b to provide a sufficiently small delay in signal transmission on these impurity layers as well as a sufficiently small voltage distribution.
However, main bit line MBL is a metal interconnection line formed above the surface of semiconductor substrate region 9, and is required to have a sufficient immunity against to a stress applied, e.g., from an interlayer insulating film, so that main bit line MBL must have a certain line width. For reducing an inter-line capacitance, a minimum value exists in inter-line distance between conductive layers 7a and 7b forming main bit lines MBL.
Further, as shown in FIG. 30, conductive layers 7a and 7b forming the main bit lines must be connected electrically to drain-side select transistors (SGD1 and SGD2) formed thereunder via contact holes 8a and 8b, respectively. Since the metal interconnection line forming the main bit line is far distant from the impurity diffusion layer at the surface of semiconductor substrate region 9, a relatively large contact region is required for making an electrical contact between conductive layers 7a and 7b forming the main bit lines and the impurity diffusion layers at the lower layer. This is because the contact resistance must be reduced, and the contact hole region must be precisely filled with a conductive material. Accordingly, as shown in FIG. 30, conductive layers 7-1 and 7-2 forming main bit lines MBL1 and MBL2 have increased line widths in the regions of contact holes 8a and 8b, respectively, and thereby the region for reliable contact is insured. A pitch of these contact regions must be ensured. Due to the above facts, the pitch of the main bit lines is, larger than the pitch in the row direction of the memory cells (i.e., pitch between the memory cells in the adjacent columns), so that the pitch of the memory cells in the row direction is restricted by the pitch of the main bit lines even if the memory cells have miniaturized structures, and therefore the memory cell area cannot be reduced.
An object of the invention is to provide a nonvolatile semiconductor memory device, in which a memory cell area can be reduced without an influence by a pitch condition of the main bit lines.
Another object of the invention is to provide a nonvolatile semiconductor memory device, in which a memory cell array area in the row direction can be significantly reduced. In summary, in a nonvolatile semiconductor memory device according to the invention, one main bit line is arranged for a plurality of columns of sub-bit lines
Since one main bit line is arranged for the sub-bit lines arranged corresponding to a plurality of columns, the pitch condition of the main bit lines can be relaxed, and the pitch of the memory cells in the row direction is not affected by the pitch condition of the main bit lines even if the memory cells are arranged at the sub-bit line pitches. Accordingly, the memory cell array can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.